In bulk substrate technology, plasma process charging damage on high antenna ratio nodes is typically prevented by the addition of diodes and gate-diode transistors. In silicon-on-insulator (SOI) technology, active SOI device regions are isolated from bulk substrates by buried oxide layers. Because SOI device regions are not directly connected to bulk substrates (i.e., there is an insulator that provides separation), SOI devices rely on equilibrium potential build up across gate and source/drain regions for process charge protection. In other words, build up charge generated during plasma processing environment is inhibited from dissipating due to an insulator region disposed on a SOI substrate. In many cases, non-equilibrium potential build up across gates and source/drain regions causes potential charging problems in scaled technologies as device dimensions continue to shrink. Additionally, as antenna ratios continue to increase, unbalanced-electron shading perturbs gate-to-channel equipotential typically resulting in higher process charging damage problems in SOI technology.